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74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
May 1991 Revised November 1998
74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ACTQ16240 utilizes Fairchild's Quiet SeriesTM technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet SeriesTM features GTOTM output control for superior performance.
Features
s Utilizes Fairchild's FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte s 16-bit version of the ACTQ240 s Outputs source/sink 24 mA s Additional specs for multiple output switching s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number 74ACTQ16240SSC 74ACTQ16240MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names OEn I0-I15 O0-O15 Description Output Enable Inputs (Active Low) Inputs Outputs
FACTTM, FACT Quiet SeriesTM, Quiet SeriesTM, and GTOTM are trademarks of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
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74ACTQ16240
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H Inputs OE3 L L H Inputs OE4 L L H
H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance
Functional Description
Outputs I0-I3 L H X O0-O3 H L Z Outputs I4-I7 L H X O4-O7 H L Z Outputs I8-I11 L H X O8-O11 H L Z Outputs I12-I15 L H X O12-O15 H L Z The ACTQ16240 contains sixteen inverting buffers with 3STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independently of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Logic Diagram
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74ACTQ16240
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature 50 mA +140C -65C to +150C -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA -20 mA +20 mA -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTTM circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C 125 mV/ns
DC Electrical Characteristics
Symbol VIH VIL VOH Minimum High Input Voltage Maximum Low Input Voltage Minimum High Output Voltage Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Output Voltage 4.5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD VOLP VOLV VOHP VOHV VIHD VILD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Max Quiescent Supply Current Minimum Dynamic Output Current (Note 3) Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum Overshoot Minimum VCC Droop Minimum High Dynamic Input Voltage Level Maximum Low Dynamic Input Voltage Level 5.0 5.0 5.0 5.0 5.0 -0.5 VOH + 1.0 VOH - 1.0 1.7 1.2 -1.0 VOH + 1.5 VOH - 1.8 2.0 0.8 V V V V V 5.0 0.5 0.8 5.5 5.5 5.5 5.5 0.6 8.0 0.1 1.0 1.5 80.0 75 -75 A mA A mA mA V 5.5 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.5 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 VIN = VIL or VIH 3.76 4.76 0.1 0.1 VIN = VIL or VIH 0.44 0.44 5.0 A V IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC - 2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min Figure 1Figure 2 (Note 5)(Note 6) Figure 1Figure 2 (Note 5)(Note 6) Figure 1Figure 2 (Note 4)(Note 6) Figure 1Figure 2 (Note 4)(Note 6) (Note 4)(Note 7) (Note 4)(Note 7) V V IOH = -24 mA IOH = -24 mA (Note 2) IOUT = 50 A V V V VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A Units Conditions
Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package. Note 5: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n - 1) outputs are switched HIGH and one output held HIGH. Note 7: Maximum number of data inputs (n) switching. (n - 1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD).
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74ACTQ16240
AC Electrical Characteristics
VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ
Note 8: Voltage Range 5.0 is 5.0V 0.5V.
TA = +25C CL = 50 pF Min 2.7 3.0 2.5 2.7 2.3 2.0 Typ 4.8 5.1 4.5 4.7 5.0 4.6 Max 7.3 7.3 7.4 7.5 7.9 7.4
TA = -40C to +85C CL = 50 pF Min 2.7 3.0 2.5 2.7 2.3 2.0 Max 7.8 7.8 7.9 8.0 8.2 7.9 ns ns ns Units
Parameter Propagation Delay Data to Output Output Enable Time Output Disable Time
(V) (Note 8) 5.0 5.0 5.0
Extended AC Electrical Characteristics
TA = -40C to +85C VCC = Com CL = 50 pF Symbol Parameter 16 Outputs Switching (Note 10) Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 9) tOSLH (Note 9) tOST (Note 9) Pin to Pin Skew HL Data to Output Pin to Pin Skew LH Data to Output Pin to Pin Skew LH/HL Data to Output 4.3 ns 2.5 ns Output Disable Time Propagation Delay Data to Output Output Enable Time 4.0 4.0 3.5 3.4 3.6 3.1 Typ Max 11.2 10.0 10.1 10.0 8.9 8.1 1.2 ns (Note 13) ns 5.6 5.6 TA = -40C to +85C VCC = Com CL = 250 pF (Note 11) Min Max 13.8 13.6 (Note 12) ns ns Units
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to LOW (tOST). Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all low-to-high, high-to-low, etc.). Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 13: The Output Disable Time is dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol CIN CPD Parameter Input Pin Capacitance Power Dissipation Capacitance Typ 4.5 30 Units pF pF VCC = 5.0V VCC = 5.0V Conditions
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74ACTQ16240
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and affect the results of the measurement. VOLP/VOLV and VOHP/VOHV: * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: * Monitor one of the switching outputs using a 50 coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. * Next decrease the input HIGH voltage level on the, VIH, until the output begins to oscillate or steps out a mins of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 14: VOHV and VOLP are measured with respect to ground reference. Note 15: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ16240
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Think Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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